Name: onnx2fpga
Title: onnx2fpga
Kind: Compiler, FPGA
Status: Running
Created: 2026-10-24 (9d ago)
Built With: Python, SystemVerilog, Verilator
Highlights:
- Compiles ONNX models into streaming dataflow FPGA accelerators
- One hardware unit per layer, joined by handshaked streams
- MLP and CNN bit exact against the integer reference under randomised backpressure (21 runs each)
- Sliding-window generators swept over 18 geometries
- Conv, Gemm, MatMul, Relu, MaxPool, Add, QDQ quantisation, skip connections
Note: Its own protobuf decoder. No onnx dependency.
Links:
Source: https://github.com/MarcosAsh/onnx2fpga
Logs: latest commits (l)
Events: <none>